Many attempts have been made to reduce spurious emissions in synthesizers of a clock distribution system. The problem is especially difficult in wideband synthesizers of a clock distribution system that operate over multiple octaves. Reducing spurious is also more difficult when using a clock distribution system with synthesizers based upon integrated circuits because shielding of different components in the synthesizer may be difficult or simply not possible.
U.S. Pat. No. 5,847,611 attempts to reduce spurious by modifying the fractional synthesizer itself. U.S. Pat. No. 6,081,022 attempts to reduce spurious by improving the clock distribution by improving shielding. Such a design may offer small improvements. U.S. Pub. No. US2011/0200076 attempts to reduce spurious with a spurious tone cancellation approach. Such a method is complex and removes the spurious after it is created. U.S. Pat. No. 5,521,533 relies on a complex approach to reduce spurious with two direct digital synthesizers (DDS). U.S. Pat. No. 8,122,277 attempts to reduce spurious with a clock distribution chip that is similar to many commercially available clock distribution chips. However, such commercially available clock distribution chips fail to provide any guidance on how to configure the chip or how to predict the location of the fractional spurious outputs. Moreover, the output fractional synthesizer is not part of the solution.